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  rev.2.00 mar 30, 2006 page 1 of 6 hd74hc377 octal d-type flip-flops (with enable) rej03d0622-0200 (previous ade-205-501) rev.2.00 mar 30, 2006 description information at the d inputs meeting the setup time requirements is transferred to the q outputs on the positive-going edge of the clock pulse if the enable input g is low. clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. when the clock input is at either the high or low level, the d input signal has no effect at the output. the circuits are designed to prevent false clocking by transitions at the g input. features ? high speed operation: t pd = 13 ns typ (c l = 50 pf) ? high output current: fanout of 10 lsttl loads ? wide operating voltage: v cc = 2 to 6 v ? low input current: 1 a max ? low quiescent supply current: i cc (static) = 4 a max (ta = 25 c) ? ordering information part name package type package code (previous code) package abbreviation taping abbreviation (quantity) hd74hc377p dilp-20 pin prdp0020ac-b (dp-20nev) p ? HD74HC377FPEL sop-20 pin (jeita) prsp0020dd-b (fp-20dav) fp el (2,000 pcs/reel) hd74hc377rpel sop-20 pin (jedec) prsp0020dc-a (fp-20dbv) rp el (1,000 pcs/reel) note: please consult the sales office for the above package availability. function table inputs outputs enable g clock data q q h x x q 0 q 0 l h h l l l l h x l x q 0 q 0 notes: 1. h ; high level, l ; low level, x ; irrelevant, ; transition from l level to h level. 2. q 0 ; the level of q before the indicated steady-state input conditions were established. 3. q 0 ; complement of q 0 or level of q before the indicated steady-state input conditions were established.
hd74hc377 rev.2.00 mar 30, 2006 page 2 of 6 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 q q q q g g g g d d d d ck ck ck ck q q q q g g g g d d d d ck ck ck ck enable g 1q v cc 8q 8d 7d 7q 6q 6d 5d 5q cloc k 1d 2d 2q 3q 3d 4d 4q gnd (top view) absolute maximum ratings item symbol ratings unit supply voltage range v cc ?0.5 to 7.0 v input / output voltage v in , v out ?0.5 to v cc +0.5 v input / output diode current i ik , i ok 20 ma output current i o 25 ma v cc , gnd current i cc or i gnd 50 ma power dissipation p t 500 mw storage temperature tstg ?65 to +150 c note: the absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. recommended operating conditions item symbol ratings unit conditions supply voltage v cc 2 to 6 v input / output voltage v in , v out 0 to v cc v operating temperature ta ?40 to 85 c 0 to 1000 v cc = 2.0 v 0 to 500 v cc = 4.5 v input rise / fall time *1 t r , t f 0 to 400 ns v cc = 6.0 v note: 1. this item guarantees maximum limit when one input switches. waveform: refer to test circuit of switching characteristics.
hd74hc377 rev.2.00 mar 30, 2006 page 3 of 6 electrical characteristics ta = 25 c ta = ?40 to+85 c item symbol v cc (v) min typ max min max unit test conditions 2.0 1.5 ? ? 1.5 ? 4.5 3.15 ? ? 3.15 ? v ih 6.0 4.2 ? ? 4.2 ? v 2.0 ? ? 0.5 ? 0.5 4.5 ? ? 1.35 ? 1.35 input voltage v il 6.0 ? ? 1.8 ? 1.8 v 2.0 1.9 2.0 ? 1.9 ? 4.5 4.4 4.5 ? 4.4 ? 6.0 5.9 6.0 ? 5.9 ? i oh = ?20 a 4.5 4.18 ? ? 4.13 ? i oh = ?4 ma v oh 6.0 5.68 ? ? 5.63 ? v vin = v ih or v il i oh = ?5.2 ma 2.0 ? 0.0 0.1 ? 0.1 4.5 ? 0.0 0.1 ? 0.1 6.0 ? 0.0 0.1 ? 0.1 i ol = 20 a 4.5 ? ? 0.26 ? 0.33 i ol = 4 ma output voltage v ol 6.0 ? ? 0.26 ? 0.33 v vin = v ih or v il i ol = 5.2 ma input current iin 6.0 ? ? 0.1 ? 1.0 a vin = v cc or gnd quiescent supply current i cc 6.0 ? ? 4.0 ? 40 a vin = v cc or gnd, iout = 0 a switching characteristics (c l = 50 pf, input t r = t f = 6 ns) ta = 25 c ta = ?40 to +85 c item symbol v cc (v) min typ max min max unit test conditions 2.0 ? ? 6 ? 5 4.5 ? ? 30 ? 24 maximum clock frequency f max 6.0 ? ? 35 ? 28 mhz 2.0 ? ? 140 ? 175 4.5 ? 13 28 ? 35 propagation delay time t plh t phl 6.0 ? ? 24 ? 30 ns 2.0 100 ? ? 125 ? 4.5 20 5 ? 25 ? setup time t su 6.0 17 ? ? 21 ? ns 2.0 5 ? ? 5 ? 4.5 5 0 ? 5 ? hold time t h 6.0 5 ? ? 5 ? ns 2.0 80 ? ? 100 ? 4.5 16 ? ? 20 ? pulse width t w 6.0 14 ? ? 17 ? ns 2.0 ? ? 75 ? 95 4.5 ? 5 15 ? 19 output rise/fall time t tlh t thl 6.0 ? ? 13 ? 16 ns input capacitance cin ? ? 5 10 ? 10 pf
hd74hc377 rev.2.00 mar 30, 2006 page 4 of 6 test circuit v cc enable g v cc z out = 50 ? pulse generator q clock d c l = 50 pf z out = 50 ? pulse generator q c l = 50 pf note : 1. c l includes probe and jig capacitance. input output input output see function table waveforms input clk gnd t plh 10 % 90 % t r 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 10 % t r 90 % 10 % t f gnd t phl v oh v cc v cc v cc v cc v ol input d output q t su t su t h gnd gnd input g input clk t r 90 % 10 % 90 % t f 10 % t f 10 % 90 % 90 % t h ? waveform ? 2  waveform ? 1 output q gnd v cc t f 10 % 90 % 50 % 50 % 50 % input g t r t f t tlh t thl 50 % t w t w t tlh t thl t plh t phl t su t h t h t su 10 % 90 % 10 % 90 % 10 % 90 % 50 % 50 % 10 % 90 % v oh v ol 90 % 10 % 90 % 10 % 1. input waveform: prr 1 mhz, zo = 50 ? , t r 6 ns, t f 6 ns note:
hd74hc377 rev.2.00 mar 30, 2006 page 5 of 6 package dimensions 7.62 max nom min dimension in millimeters symbol reference 24.50 6.30 5.08 a 1 z b 3 d e a b p c e l e 1 0.51 0.56 1.30 0.19 0.25 0.31 2.29 2.54 2.79 0 15 25.40 7.00 0.40 0.48 1.27 2.54 1 p 1 3 1 10 20 11 e b a l a z e c e d b 0.89 ( ni/pd/au plating ) p-dip20-6.3x24.5-2.54 1.26g mass[typ.] dp-20nev prdp0020ac-b renesas code jeita package code previous code 0.80 0.15 1.27 7.50 8.00 0.40 0.34 a 1 13.0 max nom min dimension in millimeters symbol reference 2.20 0.90 0.70 0.50 5.50 0.20 0.10 0.00 0.46 0.25 0.20 0.15 7.80 8 0 0.12 1.15 12.60 l 1 z h e y x c b p a 2 e d b 1 c 1 e e l a 20 11 10 f *1 *2 *3 p m x y 1 e index mark d e h b z a terminal cross section ( ni/pd/au plating ) p c b 1 1 detail f l l a note) 1. dimensions"*1 (nom)"and"*2" do not include mold flash. 2. dimension"*3"does not include trim offset. p-sop20-5.5x12.6-1.27 0.31g mass[typ.] fp-20dav prsp0020dd-b renesas code jeita package code previous code
hd74hc377 rev.2.00 mar 30, 2006 page 6 of 6 0.935 0.15 1.27 10.00 10.65 0.40 0.34 a 1 13.2 max nom min dimension in millimeters symbol reference 2.65 1.27 0.70 0.40 7.50 0.30 0.20 0.10 0.46 0.30 0.25 0.20 10.40 8 0 0.12 1.45 12.80 l 1 z h e y x c b p a 2 e d b 1 c 1 e e l a 11 20 10 f *1 *2 *3 p m x y 1 e index mark e h d z b a terminal cross section ( ni/pd/au plating ) p c b 1 1 detail f l l a note) 1. dimensions"*1 (nom)"and"*2" @ do not include mold flash. 2. dimension"*3"does not @ include trim offset. p-sop20-7.5x12.8-1.27 0.52g mass[typ.] fp-20dbv prsp0020dc-a renesas code jeita package code previous code
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology 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